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New posts in cpu-architecture
Why do we have CPUs with all the cores at the same speeds and not combinations of different speeds?
cpu
multi-core
cpu-architecture
cpu-cores
Are loads and stores the only instructions that gets reordered?
x86
cpu-architecture
memory-barriers
How many CPU cycles are needed for each assembly instruction?
performance
assembly
x86
cpu-architecture
cpu-cycles
What Every Programmer Should Know About Memory?
optimization
memory
x86
cpu-architecture
cpu-cache
Getting Processor Information
cpu
cpu-architecture
Enhanced REP MOVSB for memcpy
performance
assembly
x86
cpu-architecture
memcpy
Why doesn't "add more cores" face the same physical limitations as "make the CPU faster"?
cpu
cpu-architecture
Can x86's MOV really be "free"? Why can't I reproduce this at all?
c
assembly
x86
cpu-architecture
micro-optimization
How exactly do partial registers on Haswell/Skylake perform? Writing AL seems to have a false dependency on RAX, and AH is inconsistent
assembly
x86
intel
cpu-architecture
micro-optimization
How do I achieve the theoretical maximum of 4 FLOPs per cycle?
c++
assembly
x86-64
cpu-architecture
flops
Why doesn't GCC use partial registers?
assembly
gcc
x86
x86-64
cpu-architecture
Micro fusion and addressing modes
assembly
x86
intel
cpu-architecture
iaca
Why is the loop instruction slow? Couldn't Intel have implemented it efficiently?
performance
assembly
x86
intel
cpu-architecture
How can I enable PAE on Windows 7 (32-bit) to support more than 3.5 GB of RAM?
windows-7
memory
computer-architecture
cpu-architecture
pae
Why are newer generations of processors faster at the same clock speed?
performance
cpu
cpu-architecture
clockspeed
community-faq
What are the differences between 32-bit and 64-bit, and which should I choose?
cpu-architecture
32-bit vs. 64-bit systems
64-bit
operating-systems
32-bit
computer-architecture
cpu-architecture
Why is processing a sorted array faster than processing an unsorted array?
java
c++
performance
cpu-architecture
branch-prediction
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