New posts in memory-barriers

Are mutex lock functions sufficient without volatile?

c++ multithreading mutex volatile memory-barriers

Dependent loads reordering in CPU

synchronization locking cpu-architecture lock-free memory-barriers

Should thread-safe class have a memory barrier at the end of its constructor?

multithreading parallel-processing memory-barriers c# .net

Does std::mutex create a fence?

c++ multithreading mutex memory-barriers memory-model

Acquire/release semantics with 4 threads

c++ multithreading memory-barriers memory-model stdatomic

Why we need Thread.MemoryBarrier()?

c# .net multithreading thread-safety memory-barriers

Fastest inline-assembly spinlock

c++ assembly x86 memory-barriers spinlock

C++ Memory Barriers for Atomics

c++ windows visual-c++ memory-barriers

C++ How is release-and-acquire achieved on x86 only using MOV?

c++ x86 memory-barriers memory-model stdatomic

How do I Understand Read Memory Barriers and Volatile

multithreading volatile memory-barriers

Does it make any sense to use the LFENCE instruction on x86/x86_64 processors?

assembly x86 x86-64 atomic memory-barriers

Is function call an effective memory barrier for modern platforms?

c multithreading memory-barriers

Is there any compiler barrier which is equal to asm("" ::: "memory") in C++11?

c++ c++11 atomic lock-free memory-barriers

How does a mutex lock and unlock functions prevents CPU reordering?

c assembly x86 mutex memory-barriers

Which is a better write barrier on x86: lock+addl or xchgl?

assembly x86 memory-barriers

What's the relationship between CPU Out-of-order execution and memory order?

memory cpu cpu-architecture memory-barriers

Does an x86 CPU reorder instructions?

multithreading assembly x86 cpu-architecture memory-barriers

Why do I need a memory barrier?

c# multithreading thread-safety shared-memory memory-barriers

Does a memory barrier ensure that the cache coherence has been completed?

assembly x86 operating-system cpu-cache memory-barriers

How is load->store reordering possible with in-order commit?

arm cpu-architecture memory-barriers