Newbetuts
.
New posts in memory-barriers
Why is (or isn't?) SFENCE + LFENCE equivalent to MFENCE?
assembly
x86
x86-64
memory-barriers
memory-fences
When should I use _mm_sfence _mm_lfence and _mm_mfence
c++
multithreading
x86
intrinsics
memory-barriers
Does the Intel Memory Model make SFENCE and LFENCE redundant?
assembly
optimization
x86
atomic
memory-barriers
Atomicity on x86
c++
multithreading
x86
atomic
memory-barriers
Memory barrier generators
c#
memory-barriers
Synchronizing caches for JIT/self-modifying code on ARM
assembly
arm64
cpu-cache
memory-barriers
self-modifying
Are loads and stores the only instructions that gets reordered?
x86
cpu-architecture
memory-barriers
Prev