Newbetuts
.
New posts in x86
What's the relative speed of floating point add vs. floating point multiply
floating-point
x86
mips
numerical-computing
flops
Do current x86 architectures support non-temporal loads (from "normal" memory)?
c++
caching
x86
cpu-cache
prefetch
X86 Solaris boot failure
solaris
grub
x86
Getting cpu cycles using RDTSC - why does the value of RDTSC always increase?
linux
assembly
x86
cpu-usage
rdtsc
What does "DS:[40207A]" mean in assembly?
assembly
x86
memory-address
disassembly
memory-segmentation
What does jmp ds:dword mean [duplicate]
assembly
x86
memory-address
disassembly
memory-segmentation
Fastest inline-assembly spinlock
c++
assembly
x86
memory-barriers
spinlock
Why do VirtualBox guest kernels run in ring 1 instead of ring 3?
virtualbox
virtualization
x86
Why is linear read-shuffled write not faster than shuffled read-linear write?
python
performance
numpy
x86
cpu-cache
How to flush the CPU cache for a region of address space in Linux?
c
linux
linux-kernel
x86
arm
What does MOV EAX, DWORD PTR DS:[ESI] mean and what does it do?
assembly
x86
Why is gcc allowed to speculatively load from a struct?
c
gcc
assembly
x86
compiler-optimization
Weird MSC 8.0 error: "The value of ESP was not properly saved across a function call..."
c++
visual-c++
x86
stack
calling-convention
How does x86 pause instruction work in spinlock *and* can it be used in other scenarios?
multithreading
x86
cpu-architecture
instructions
spinlock
How are atomic operations implemented at a hardware level?
language-agnostic
x86
atomic
smp
What does ORG Assembly Instruction do?
assembly
x86
nasm
directive
"enter" vs "push ebp; mov ebp, esp; sub esp, imm" and "leave" vs "mov esp, ebp; pop ebp"
assembly
x86
stack
micro-optimization
stack-frame
Cycles/cost for L1 Cache hit vs. Register on x86?
performance
x86
cpu-architecture
cpu-cache
micro-optimization
Performance-impact of Hyper-Threading
performance
intel-core-i7
intel-core-i5
x86
hyper-threading
Dividing in assembly ax and bx [duplicate]
assembly
x86
x86-16
tasm
dosbox
Prev
Next