What is the best way to implement a DEMUX using VHDL?

Well, I am learning some basics about digital circuits, and suffice to say I am just a beginner. For my final project, I have to implement some components and one of them is a demultiplexer. Actually, I think there must be better ways to implement it and I think my code is not clean. Is there a way to implement it using a for loop or a while? Here is my code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;



entity Demux17 is
    Port ( I : in  STD_LOGIC;
           SEL : in  STD_LOGIC_VECTOR (4 downto 0);
           O : out  STD_LOGIC_VECTOR (16 downto 0));
end Demux17;

architecture Behavioral of Demux17 is

begin
    O(0) <= (I AND NOT SEL(0) AND NOT SEL(1) AND NOT SEL(2) AND NOT SEL(3) AND NOT SEL(4));
    O(1) <= (I AND SEL(0) AND NOT SEL(1) AND NOT SEL(2) AND NOT SEL(3) AND NOT SEL(4));
    O(2) <= (I AND NOT SEL(0) AND SEL(1) AND NOT SEL(2) AND NOT SEL(3) AND NOT SEL(4));
    O(3) <= (I AND SEL(0) AND SEL(1) AND NOT SEL(2) AND NOT SEL(3) AND NOT SEL(4));
    O(4) <= (I AND NOT SEL(0) AND NOT SEL(1) AND SEL(2) AND NOT SEL(3) AND NOT SEL(4));
    O(5) <= (I AND SEL(0) AND NOT SEL(1) AND SEL(2) AND NOT SEL(3) AND NOT SEL(4));
    O(6) <= (I AND NOT SEL(0) AND SEL(1) AND SEL(2) AND NOT SEL(3) AND NOT SEL(4));
    O(7) <= (I AND SEL(0) AND SEL(1) AND SEL(2) AND NOT SEL(3) AND NOT SEL(4));
    O(8) <= (I AND NOT SEL(0) AND NOT SEL(1) AND NOT SEL(2) AND SEL(3) AND NOT SEL(4));
    O(9) <= (I AND SEL(0) AND NOT SEL(1) AND NOT SEL(2) AND SEL(3) AND NOT SEL(4));
    O(10) <= (I AND NOT SEL(0) AND SEL(1) AND NOT SEL(2) AND SEL(3) AND NOT SEL(4));
    O(11) <= (I AND SEL(0) AND SEL(1) AND NOT SEL(2) AND SEL(3) AND NOT SEL(4));
    O(12) <= (I AND NOT SEL(0) AND NOT SEL(1) AND SEL(2) AND SEL(3) AND NOT SEL(4));
    O(13) <= (I AND SEL(0) AND NOT SEL(1) AND SEL(2) AND SEL(3) AND NOT SEL(4));
    O(14) <= (I AND NOT SEL(0) AND SEL(1) AND SEL(2) AND SEL(3) AND NOT SEL(4));
    O(15) <= (I AND SEL(0) AND SEL(1) AND SEL(2) AND SEL(3) AND SEL(4));
    O(16) <= (I AND NOT SEL(0) AND NOT SEL(1) AND NOT SEL(2) AND NOT SEL(3) AND SEL(4));
end Behavioral;

I will be grateful for any help or advice. Thanks.

Try something with a generate-statement using your SEL input as an address for the O output

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity Demux17 is
    Port ( I : in  STD_LOGIC;
           SEL : in  STD_LOGIC_VECTOR (4 downto 0);
           O : out  STD_LOGIC_VECTOR (16 downto 0));
end Demux17;

architecture Behavioral of Demux17 is

begin
   gen_label: for J in 0 to 16 generate
      O(J) <= I when to_integer(unsigned(SEL)) = J else '0';
   end generate gen_label;
end Behavioral;