Does the M1 Chip Support Second Level Address Translation (SLAT)?

I am trying to understand if the new M1 Macs support Second Level Address Translation (SLAT) or if a similar technology is called something different in Apple's interpretation of this specification?

"Second Level Address Translation" is known as "Stage-2 page tables" in the ARM world. It's not an Apple specific term, but rather a general one for the ARM architecture.

The M1 has got Stage-2 page tables, so it does have SLAT.

The M1 CPU features the ARMv8.4-A instruction set and VHE, virtualization host extensions. The CPU features exception level 0-2, which is means that you can have the hypervisor running in level 2, while the guest operating system are at level 1 and their user space's at level 0. Stage-2 page tables ensures that it you can efficiently handle page table mappings when switching between guests. ARM requires Stage-2 page tables when implementing EL2.

The M1 notably does not feature EL3, and it is a bit unconventional in always enabling VHE.