When a CPU sends an address to memory

In ancient times (1970's and 1980's) that's pretty close to how things generally worked. Essentially, the computer's memory bus would comprise a number of address wires (typically 16, 20, 24, or 32), some number of data wires (typically 8, 16, or 32), and a few control signals. There were a few variations on the control signals, but the typical pattern was that for a read the processor would put an address on the address bus, float the data bus (allowing other devices to drive it), set the control signals in a fashion indicating a memory read, and some time later take whatever signals are on the address bus as the read data, and then release the control signals. For a write, the processor would put the address on the address bus, set the control signals to indicate a write, put the proper data on the data bus, release the control signals indicating a write, and then float the data bus. Some processors allow I/O accesses, which are similar to memory accesses except for special wires which indicate whether a given access is a memory or I/O access.

Typically, the system would have a number of memory or peripheral devices connected to the memory bus, each with a chip-select signal connected to some decoder logic. The decoder logic would assert each chip-select signal whenever a certain range of memory or I/O addresses is selected. Each chip will ignore the contents of the address and data buses except when its chip-select wire is asserted.

Starting in the 1990's (to some slight extent before that), systems added a few more layers between the processors and the memory system. Today's processor memory systems would probably be unrecognizable to people who were only familiar with the ones from the 1980's.