Typedef Enum - Instantiation at top module and port connection
Solution 1:
Here is one way to get rid of the compile errors:
module top (
output logic DEBUG_1,
output logic DEBUG_2, DEBUG_3
);
// ... signal declarations
fsm fsm_inst (
.clk (sys_clk),
.reset (sys_reset),
.state ({DEBUG_3, DEBUG_2, DEBUG_1})
);
endmodule
Concatenate the 3 DEBUG bits using {}, then connect it directly to the state port.