What is the meaning of full-width link and half-width link in peripheral specifications of CPU/microprocessors?
I am studying the bus characteristics of microprocessors for a seminar that is part of a course of computing system foundations that I am taking at the university. I am studying Intel Itanium. In this website I found the following description (I am just showing the part I am interested in) about one of the processors in this family:
Intel Itanium 2 9310
Integrated Peripherals and Components:
Other Peripherals:
- Two DDR3 memory controllers
- Quick Path Interconnect with 4 full-width and 2 half-width links
I read a bit about Quick Path Interconnect, but I was not able to discover the meaning of full-width and half-width links.
Can anyone tell me what full-width and half-width links mean in this context?
Thanks in advance.
From the Intel Quick Path Interconnect Introduction Whitepaper, in the Physical Layer section:
Each full link is comprised of twenty 1-bit lanes that use differential signaling and are DC coupled.
At full-width that would be 20 bits, at half-width 10 bits and at quarter-width 5 bits.
If, for whatever reason, a link is unable to be established at full-width then it appears that the interconnect can negotiate down to whatever link width is available.