How to properly instantiate a module and pass registers to it
[![Simulation: modules seem to be running but not passing/recieving appropriate info?][1]][1]
I'm trying to become familiar with the Xilinx iSim utility. I am comfortable simulating a single, self contained module. However, when I begin introducing and instantiating multiple modules, I get unexpected results. The lower module BCD_sevseg does not appear to be accepting any input as it's clock will not cycle at all, let alone in sync with the top module clock
I am unsure of exactly how to structure the test bench but I'm sure there is a more fundamental issue with my understanding of what I'm trying to accomplish. However, previous attempts with similar structures implemented perfectly fine and my FPGA operated as expected.
I've verified the appropriate values are passed in an appropriate order and I don't receive any errors or warning upon a syntax check or simulation.
My top module is "instantiating" (is this the correct word) the BCD_sevseg module as follows
BCD_sevseg is supposed to accept clk (probably bad practice), a four bit number, and return the appropriate combination of LED states for the equivalent decimal number
There's most likely a lot of "accepted practices" I'm violating here, but I'm really just trying to get the test bench to operate properly at the moment.
I believe these are the requested modules.
TEST BENCH
`timescale 1ns / 1ps
module mod_10_II_sim;
reg clk;
reg clock;
reg [3:0] bin_sevseg_value;
wire led_a;
wire led_b;
wire led_c;
wire led_d;
wire led_e;
wire led_f;
wire led_g;
wire a;
wire b;
wire c;
wire d;
wire e;
wire f;
wire g;
BCD_sevseg inst_one(
.clock(clock),
.bin_sevseg_value(bin_sevseg_value),
.a(a),
.b(b),
.c(c),
.d(d),
.e(e),
.f(f),
.g(g)
);
mod_10_top uut (
.clk(clk),
.led_a(led_a),
.led_b(led_b),
.led_c(led_c),
.led_d(led_d),
.led_e(led_e),
.led_f(led_f),
.led_g(led_g)
);
initial begin
clk = 0;
clock = 0;
bin_sevseg_value = 0;
#100;
end
always #10 clk = ~clk;
endmodule
TOP MODULE
`timescale 1ns / 1ps
module BCD_sevseg( clock, bin_sevseg_value, a, b, c, d, e, f, g);
input clock;
input [3:0] bin_sevseg_value;
output a;
output b;
output c;
output d;
output e;
output f;
output g;
reg A = 1'b0;
reg [0:0] B;
reg [0:0] C;
reg [0:0] D;
reg [0:0] E;
reg [0:0] F;
reg [0:0] G;
assign a = A;
assign b = B;
assign c = C;
assign d = D;
assign e = E;
assign f = F;
assign g = G;
always @(posedge clock) begin
case (bin_sevseg_value)
4'b0000: begin
A <= 1;
B <= 1;
C <= 1;
D <= 1;
E <= 1;
F <= 1;
G <= 0;
end
4'b0001: begin
A <= 0;
B <= 1;
C <= 1;
D <= 0;
E <= 0;
F <= 0;
G <= 0;
end
4'b0010: begin
A <= 1;
B <= 1;
C <= 0;
D <= 1;
E <= 1;
F <= 0;
G <= 1;
end
4'b0011: begin
A <= 1;
B <= 1;
C <= 1;
D <= 1;
E <= 0;
F <= 0;
G <= 1;
end
4'b0100: begin
A <= 0;
B <= 1;
C <= 1;
D <= 0;
E <= 0;
F <= 1;
G <= 1;
end
4'b0101: begin
A <= 1;
B <= 0;
C <= 1;
D <= 1;
E <= 0;
F <= 1;
G <= 1;
end
4'b0110: begin
A <= 1;
B <= 0;
C <= 1;
D <= 1;
E <= 1;
F <= 1;
G <= 1;
end
4'b0111: begin
A <= 1;
B <= 1;
C <= 1;
D <= 0;
E <= 0;
F <= 0;
G <= 0;
end
4'b1000: begin
A <= 1;
B <= 1;
C <= 1;
D <= 1;
E <= 1;
F <= 1;
G <= 1;
end
4'b1001: begin
A <= 1;
B <= 1;
C <= 1;
D <= 1;
E <= 0;
F <= 1;
G <= 1;
end
default: begin
A <= 0;
B <= 1;
C <= 1;
D <= 0;
E <= 1;
F <= 1;
G <= 1;
end
endcase
end
endmodule
module mod_10_top( clk, led_a, led_b, led_c, led_d, led_e, led_f, led_g );
input clk;
output led_a;
output led_b;
output led_c;
output led_d;
output led_e;
output led_f;
output led_g;
reg [9:0] counter;
reg [3:0] seven_segment_digit;
assign led_a = state_a;
assign led_b = state_b;
assign led_c = state_c;
assign led_d = state_d;
assign led_e = state_e;
assign led_f = state_f;
assign led_g = state_g;
/*-------------END DECLARATIONS----------------*/
BCD_sevseg inst_one( clk, seven_segment_digit, state_a, state_b, state_c, state_d, state_e, state_f, state_g);
always @(posedge clk) begin
counter <= counter + 1;
end
always @(posedge counter[8]) begin
for(seven_segment_digit = 4'b0000; seven_segment_digit < 4'b1010; seven_segment_digit = seven_segment_digit + 4'b0001) begin
end
end
endmodule
[1]: https://i.stack.imgur.com/1mJBH.png
Solution 1:
You connected the wrong signal to the BCD_sevseg instance in the testbench module mod_10_II_sim. In the testbench, you only toggle the clk signal, but not the clock signal.
Change:
BCD_sevseg inst_one(
.clock(clock),
to:
BCD_sevseg inst_one(
.clock(clk),
You should see a clock toggling in all instance of all modules.
Note: you should explicitly declare all your state_ signals because my simulator gave me compile errors.
wire state_a;
wire state_b;
// etc.