VHDL Increment Signal doesn't work properly

Solution 1:

Your code is syntactically correct, and will increment Q_int by the required amount. The problem is that Q_int is initialised to "UUUU" and is not assigned a value on reset. And when you add anything to "UUUU", you get "UUUU".

The answer here is to either: Give Q_int and initial value: eg.

signal Q_int : std_logic_vector(3 downto 0) := "0000";

or assign Q_int a value when reset occurs

if RESET ='1' then
  Q_int <= "0000";
  --etc

The second case will also avoid the reset->clock enable connection you will have created by not resetting Q_int when Q is reset.

On a side note, you are using non-standard VHDL library std_logic_unsigned . It is recommended that you stick to standard vhdl library numeric_std and use the unsigned type, or with VHDL 2008 you can use the ieee.numeric_std_unsigned package, that allows you to use std_logic_vector as a numerical unsigned value.

Solution 2:

signal Q_int : std_logic_vector(3 downto 0) := (others => "0");

You should just initialize your signal you can do it on the top module or in test bench it self .