VHDL ERROR: formal port 'num' has no actual or default value
Solution 1:
To your problem is just that you don't use the proper syntax for port mapping your this is the correct syntax
uut : testing_logic
port map(
num =>num_TB,
btn_add => btn_add_TB,
btn_sub => btn_sub_TB,
clk => clk_TB,
reset => reset_TB,
led => led_TB
);