Testing multiple configurations of parameterizable modules in a Verilog testbench
Since $value$plusargs
is evaluated at runtime, it can not be used to set parameter
values, which must be done at compile-time.
However, if you use generate
to instantiate multiple instances of the design with different parameter
settings, you might be able to use $value$plusargs
to selectively activate or enable one instance at a time. For example, in the testbench, you could use the runtime argument to only drive the inputs of a specific instance.