A 4-bit counter D flip flop with + 1 logic

You have 2 different always blocks which drive the same register Q. you can think of a separate always block as a separate hardware device. So, in your case, you have 2 flop outputs of which are connected. This violates hardware and synthesis rules. It also creates issues during simulation.

The only way to fix it is to create a single always block which defines all logic needed to drive the flop, something like the following:

always @ (posedge clk or negedge clear) begin
    if (!clear)
        Q <= 1'b0;
    else if (enable)
        Q <= D + 1;
    else 
        Q <= D;
end

I am not commenting on you logic here, just giving an example which should eliminate all errors around multiple drivers for Q.