How does signal assignment work in a process?
Solution 1:
Variables get updated as you assign them. Signals get update in the next delta cycle (at the earliest).
a := '1'; -- variable
assert a = 1;
b <= '1'; -- signal
computationUsing(b); --reads old value of b
-- new value will be visible after this process ends or some time passes
Jan Decaluwe explains this stuff in more detail here: http://www.sigasi.com/content/vhdls-crown-jewel
Solution 2:
The way it works:
Y
changes and the process begins.
X
will be assigned to what Y's value
currently is, but not until the end of the process
Z
will be assigned to not X's old value
but not until the end of the process
The process ends so now X
and Z
will be updated