Clarification of the difference between PCI memory addressing and I/O addressing?

Solution 1:

The physical address space is huge nowadays due to 64 bit addressing. Many devices, for example AHCI-compliant disk controllers, require quite big chunks of address space to be mapped to the device registers.

Also, the IO address space is not accessible with usual assembler instructions. It is accessible only with special instructions that can read from and write to the IO ports. This is not really convenient and inefficient in many cases.

For example the above mentioned ACPI compliant controller has some functionality that requires the processor to execute locked read-modify-write operation to change a single bit in a device register provided no other cores will be able access and modify the same register in between. With IO address space this is not possible at all.

One more point we should take to account is that the PCI bus is not unique to the x86 architecture. There are other architectures exist that has no special IO bus at all. So the device vendors prefer not to use IO addresses to stay compatible with most systems. Thus no one is using the IO address space. Then why not make de-jure the thing that is de-facto for a long time already?