RISC-V: Implementing SLLI, SRLI and SRAI
You can find the answer directly in the RISC-V specifications.
imm[11:5] imm[4:0] rs1 func3 rd opcode inst
------------------------------------------------------------
0000000 shamt rs1 001 rd 0010011 SLLI
0000000 shamt rs1 101 rd 0010011 SRLI
0100000 shamt rs1 101 rd 0010011 SRAI
As for the latency, the ISA only deals with architectures not micro-architectures.
That means that two RISC-V conforming CPUs can execute a shift in a different number of clock cycles.