Can someone explain to me how the CPU finds the source of an interrupt in OS theory?

I am currently doing a module in Operating Systems theory and I have a few concepts that I am unable to grasp - would this be the right place to ask questions ?

My main question is about interrupts. When the CPU detects that there has been an interrupt, I understand that it must find out where this interrupt originated. My understanding is as follows, could anyone tell me if this is correct, and explain a few gaps in my knowledge ?

For the CPU to detect where the interrupt originated, it could query all objects to identify the source, but these I/O based questions would take a long time. Instead, it uses the interrupt cycle, and expects an interrupt identifier on the data bus. If it is an 8 bit data bus, there is 256 interrupt levels (i.e 2^8). (Why is this?)

So an Interrupt Service Routine (ISR) is written for every possible interrupt level and stored in a table at a fixed location (interrupt vector) which is standardized by the processor. In my notes is says "Location must be known before getting the address" (What does this mean?)

The interrupt level identifier received as part of the interrupt cycle is used as an index into the interrupt vector (Can someone break this down a little please?). My understanding is that a value, the interrupt level identifier is passed to the CPU and used to point at the interrupt vector.

Also, what does it mean when an interrupt is said to be "serviced"?

Thank you very much, and sorry for the long paragraphs, I am just a little confused by many aspects of this !

Solution 1:

what does it mean when an interrupt is said to be "serviced"?

When the thing requesting the interrupt is taken care of, then it is called "serviced." This could be as simple as reading the next character from the keyboard, or sending the next packet of data out the ethernet card. Some interrupts are more important than others, so there is the capability to prioritize them.

A useful article can be found here.

The interrupt level identifier received as part of the interrupt cycle is used as an index into the interrupt vector

As you mentioned, when an interrupt happens, the CPU basically asked "who did that?" and the interrupting device puts its interrupt identifier on the data bus. The CPU then takes this number and looks it up into the table of ISR to transfer execution to the handler.

An interrupt is a request of the processor to suspend its current program and transfer control to a new program called the Interrupt Service Routine (ISR). Special hardware mechanisms that are designed for maximum speed force the transfer. The ISR determines the cause of the interrupt, takes the appropriate action, and then returns control to the original process that was suspended.

Solution 2:

Instead, it uses the interrupt cycle, and expects an interrupt identifier on the data bus. If it is an 8 bit data bus, there is 256 interrupt levels (i.e 2^8). (Why is this?)

The alternative to doing that is to have a pin on the CPU for each IRQ type or level you want to support. The 68000 did this, they had 3 interrupt pins allowing you to express IRQ level 0 (NMI) through 7. Intel CPUs only have 1 IRQ pin and expect an address on the bus (provided by an intermediate device called the PIC) to provide its type (I think on Intel this "address", really an index, goes directly into a register. Some PICs can actually tell the CPU what address to go to directly).

I believe they have a separate NMI pin (and there are other interrupts with their own pins such as SMI, IPI, and a reset is a type of interrupt).

So an Interrupt Service Routine (ISR) is written for every possible interrupt level and stored in a table at a fixed location (interrupt vector) which is standardized by the processor.

You don't need to write 256 ISRs, you can create a "stub" that simply "returns from interrupt", effectively ignoring it.

In my notes is says "Location must be known before getting the address" (What does this mean?)

It's a bit ambiguous - I don't know if it means you need to know the base address of the vector table or simply saying you can't know the address of the ISR if you don't know the IRQ number involved.

The interrupt level identifier received as part of the interrupt cycle is used as an index into the interrupt vector (Can someone break this down a little please?).

PIC receives an IRQ from a device. This device is set to trigger IRQ #3. CPU, upon receiving the IRQ from the PIC, sees 3 on the bus, and jumps to the address in its local IRQ vector table, index 3.

My understanding is that a value, the interrupt level identifier is passed to the CPU and used to point at the interrupt vector.

Right.

Also, what does it mean when an interrupt is said to be "serviced"?

Typically you don't want the CPU interrupted while it's handing an interrupt. CPUs and CPU + PIC combinations do various things to disable interrupts after an IRQ is received. So you have to "announce" when you're done handling it. On Intel you have to reenable the system interrupt-enable bit, and tell the PIC you are done servicing the IRQ. The PIC "holds back" further IRQs until the CPU tells it that it's done.

I've left out some details from the above to simplify and also because it's been a long time since I've studied any of the above, but I hope it is helpful.