How to understand lspci tree format?

I use a Dell G3 3579 to run the lspci -tvv command.

Here is the output:

-[0000:00]-+-00.0  Intel Corporation 8th Gen Core Processor Host Bridge/DRAM Registers
           +-01.0-[01]----00.0  NVIDIA Corporation GP106M [GeForce GTX 1060 Mobile]
           +-02.0  Intel Corporation Device 3e9b
           +-04.0  Intel Corporation Xeon E3-1200 v5/E3-1500 v5/6th Gen Core Processor Thermal Subsystem        
           +-08.0  Intel Corporation Xeon E3-1200 v5/v6 / E3-1500 v5 / 6th/7th Gen Core Processor Gaussian Mixture Model
           +-12.0  Intel Corporation Cannon Lake PCH Thermal Controller
           +-14.0  Intel Corporation Cannon Lake PCH USB 3.1 xHCI Host Controller
           +-14.2  Intel Corporation Cannon Lake PCH Shared SRAM
           +-14.3  Intel Corporation Wireless-AC 9560 [Jefferson Peak]
           +-15.0  Intel Corporation Device a368
           +-15.1  Intel Corporation Device a369
           +-16.0  Intel Corporation Cannon Lake PCH HECI Controller
           +-17.0  Intel Corporation 82801 Mobile SATA Controller [RAID mode]
           +-1b.0-[02-3a]--
           +-1d.0-[3b]----00.0  Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller
           +-1f.0  Intel Corporation Device a30d
           +-1f.3  Intel Corporation Cannon Lake PCH cAVS
           +-1f.4  Intel Corporation Cannon Lake PCH SMBus Controller
           \-1f.5  Intel Corporation Cannon Lake PCH SPI Controller

I know that the GPU is directly connect to the CPU through the PCIE and intel use PCH to connect other devices.

Here are the questions:
Q1: Why the tree output shows that all the devices connect to the same PCI bus(bus 00)?
Q2: What does +-1b.0-[02-3a]-- mean?
Q3: How do I know which device is connect to CPU's PCI-E or PCH's PCI-E bus?

Solution 1:

Why the tree output shows that all the devices connect to the same PCI bus(bus 00)?

Because that's how PCIe structure works: All devices are connected to a single root node. (Though you can have several PCIe domains, but that complicates things).

For Intel, all external PCIe lanes, no matter if they originate from the CPU or the PCH, are behind PCIe bridges (and therefore get new PCIe bus numbers). The devices in the PCH southbridge itself show up as direct descendants of the PCIe root.

Remember that the CPU and PCH are closely coupled through a proprietary high-speed bus, which is transparent to the PCIe protocol. That's why the PCIe layout doesn't match the physical layout.

What does +-1b.0-[02-3a]-- mean?

1b.0 is a slot and function number of the PCIe root hub. In this case, it contains a PCIe bridge. The busses behind this bridge would be numbered 02 to 3a, even though there are currently no devices attached to them.

In a similar way, your GPU is behind the bridge 01.0, and your LAN controller behind the bridge 1d.0, which may be an internal bridge.

How do I know which device is connect to CPU's PCI-E or PCH's PCI-E bus?

Typically they would show up behind different PCIe bridges. Details depend on the Intel CPU architecture. No, I don't know what bridges that would be for your particular architecture, but possibly one can find out with Intel datasheets and/or by observing existing systems.